Most integrated circuits include a clock network for providing a clock signal to various synchronized circuitry. The clock network typically includes one or more clock sources that are coupled to one or more clock "sinks." A clock sink is any circuit requiring a clock. Examples of sinks include flip-flops, state machines, and counters.
It is typically desired that clocks routed within the integrated circuit be synchronized, such that each clocked device receives the same clock signal at approximately the same time. This ensures that data leaving a clocked source device arrives on time to its clocked destination device.
A phenomenon known as "clock skew," wherein various clock signals arrive at clock sinks at different times, can greatly affect the synchronization. Clock skew is caused by differences in interconnect delays between various clock wires routed through the integrated circuit. The interconnect delay is directly proportional to the following quantities: EQU t.sub.delay .varies.R.sub.wire *(C.sub.wire +C.sub.load)
It can therefore be appreciated that in order to minimize clock skew, the resistance (e.g., R.sub.wire) and capacitance of all of the clock wires (e.g., C.sub.wire) and the capacitance of all of the clock loads (e.g., C.sub.load) need to be equalized. Because the wire resistance and capacitance are dependent upon the length of the wire, it is important in routing a clock singal that clock wires lengths are as close to equal as possible. Moreover, it is also important that the load capacitance coupled to each clock wire is equalized as much as possible.
Allowable clock skew is typically a parameter that is set by a designer of a circuit as a percentage of the cycle time of the synchronized components of the system. A typical clock skew may be set at 10% of the cycle time, the cycle time being the inverse of clock frequency. Thus it can be appreciated that as frequencies of integrated circuits, such as high speed microprocessors, increase, the cycle time decreases. The amount of allowable skew therefore becomes smaller.
While reducing clock skew is an important objective in designing high-frequency integrated circuits, there are other parameters that are also taken into consideration during the circuit design process. For instance, as frequencies increase, and high density circuits are developed with an increased number of loads in integrated circuits, the amount of power consumed by the integrated circuit becomes quite large. It is therefore desirable to provide a clock routing technique that not only reduces clock skew, but also decreases an amount of power consumed by the integrated circuit. Moreover, clock rise and fall time is proportional to both line resistance and load capacitance, so it is desirable to reduce the line resistance and load capacitance in designing a low-skew clock tree.
One objective of circuit designers has been to construct a clock tree for connecting clock source to clock destinations, whereby the paths from each clock sink to the clock source are equal. One prior way of reducing clock skew involves routing an equal path length clock tree by manually producing a layout for every clock wire within the integrated circuit. While this method involved a great deal of flexibility in integrated circuit design, such customization is time consuming and costly. Therefore, prior art methods were developed to automatically produce clock networks with computer software.
FIGS. 1a-1c illustrate a variety of prior art clock trees which may be automatically designed (i.e. computer-generated) to minimize clock skew. FIG. 1a is an H-tree clock network. The H-tree couples a clock source 115 to clock sinks (represented as dots), such as clock sink 112. The H-tree in FIG. 1a has one upper level H-shaped tree 110 along with 4 lower level H-shaped subtrees such as subtree 111. As shown, the path from clock source 115 to all of the clock sinks is equal. Therefore the H-tree has the advantage of providing zero skew. The H-tree has one disadvantage, however, in that the clock sinks must be uniformly placed on the integrated circuit in order to facilitate a zero skew H-tree. This is a design constraint that can lead to increased die space, complexity, and engineering time, thus increasing the design cost of the integrated circuit.
FIG. 1b illustrates another prior art clock tree. This clock tree has a thick clock trunk 120 coupled to a clock source 125. Because wire resistance (e.g., R.sub.wire) is inversely proportional to wire width, the thick clock trunk 120 exhibits a decreased resistance. The delay time for a clock signal to travel on the clock trunk 120 to the clock branches is therefore correspondingly decreased. The clock branches such as clock branch 121 extend to clock sinks 122. Each of clock sinks 122 is not equidistant from the clock source 125.
The design of the clock tree of FIG. 1b is especially well-suited for standard cell designs, in which a standard cell such as cell 123 is repeated many times. An example of a standard cell design is a memory array. The branches 121 extended from the clock trunk 120 are of equal length and equally spaced apart, thus making the clock skew among each of the cells uniform. There are two disadvantages to this type of clock tree system. First, as mentioned above, the path from the source 125 to each clock sink is not equal. Some clock skew will therefore be present. Second, in order for the clock tree to minimize skew, the clock sinks must be spaced in a symmetric fashion, creating design constraints and thereby increasing the cost of design.
The "clock trunk" design of FIG. 1b may alternatively be implemented with more than one clock trunk (i.e. clock trunk 120) strategically placed within the circuit design.
FIG. 1c illustrates a third prior art clock tree. The tree of FIG. 1c is a wire grid structure 130 coupled to a clock source 135. Each clock sink 132 is then coupled to one wire of the clock grid. This arrangement has the advantage of not requiring that clock sinks be symmetrically placed within the circuit layout. However, this design is disadvantageous in that does not provide for an equal path length between the source and clock sinks. Therefore, the clock tree has skew problems.
Other prior art clock trees are designed with equal path lengths, but are not "planar." In other words, in these clock trees, two wires may cross in order to ensure an equal path length. The problem with a non-planar clock tree is that the two wires that cross over each other must be routed in different layers of the integrated circuit. Thus, a large interconnect delay will be encountered by a clock signal traveling through a contact or via to a different metal layer. Non-planar clock trees are therefore undesirable because they exhibit clock skew, despite the fact that the clock tree employs equal path lengths.
What is desired, therefore, is a clock tree that will reduce an amount of clock skew. Moreover, it is desired to provide a clock tree that will consume less power than current methods and provide a desirable rise and fall time of the clock signals.